cMIPS - a VHDL model for the 5-stage pipeline, MIPS32r2 core

pipeline cMIPS is a model in VHDL that mimics the pipeline design described in Patterson & Hennessy's book (Computer Organisation and Design) and is intended to be a complete implementation of the MIPS32r2 instruction set. Currently there are a few opcodes missing, mostly to do with the Control Processor (COP0).

The processor executes code generated by the GCC toolset without changes. An stdlib lookalike is in the works, as well as a port of embedded Linux.

The floating point instructions are being implemented, and a TLB plus assorted control registers will be added soon (as of march 2015).

The project is hosted here. A more complete description can be found at docs/cMIPS.pdf, in the repository.

Last revision: 16mar15
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