The Performance of SCI Multiprocessor Rings

Abstract

The Scalable Coherent Interface (SCI) is an IEEE standard that defines a hardware platform for scalable shared-memory multiprocessors. This paper contains a quantitative performance evaluation of an SCI-connected multiprocessor that assesses both the communication and cache coherence subsystems. For the architecture and workload simulated, it was found that the largest efficient ring size is eight nodes and that raw network bandwidth seen by a processing element is limited at about 80Mbytes/s. A qualitative comparison to the DASH multiprocessor is also presented.