--== Header =============================================================================

library IEEE;
use IEEE.std_logic_1164.all;

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--== Entidade ===========================================================================

ENTITY alarm IS
	PORT (
		signal      cc :  IN std_logic;
		signal       m :  IN std_logic;

		signal      clk :  IN std_logic;
		signal    reset :  IN std_logic;

		signal  sirene : OUT std_logic
	);
END alarm;

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--== Arquitetura ========================================================================

ARCHITECTURE behavior OF alarm IS
	-- Sinais Locais
	--signal e0 :std_logic;
	--signal e1 :std_logic;
	
	signal es :std_logic_vetor(3 downto 0);


-- Comportamento
BEGIN
	process(clk,reset)
	begin
		if reset='1' then
			--e0 <= '0';
			--e1 <= '0';
		elsif rising_edge(clk) then  
			--e0 <= ((not e1)and(not e0)and cc) or ((((not e1) and (e0)) and cc) and (not m));
			--e1 <= (((not e1 and e0) and cc) and m) or (e1 and cc);



			case es & cc &
				when "0000" =>    es<="00"; sirene <='0'; 
				when "0001" =>    es<="00"; sirene <='0'; 
				when "0010" =>    es<="00"; sirene <='0'; 
				when "0011" =>    es<="00"; sirene <='0'; 
				...
			end case;
		end if;
	end process;


	sirene <= e1;

END;

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