--== Header =============================================================================

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

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--== Entidade ===========================================================================

ENTITY alarm_tb IS
END alarm_tb;

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--== Arquitetura ========================================================================

ARCHITECTURE behavior OF alarm_tb IS
	-- Sinais Locais
	signal state : std_logic_vector(1 downto 0);

	signal     ss : std_logic_vector(2 downto 0);
	signal      m : std_logic;
	signal     cc : std_logic;
	signal sirene : std_logic;

	signal   clk : std_logic;
	signal reset : std_logic;

	-- Usando a definicao dos seguintes componentes
 component analisa IS
	-- Parte 1.1
	 PORT (
	   signal s2 : IN std_logic;
	   signal s1 : IN std_logic;
	   signal s0 : IN std_logic;
	  signal m : OUT std_logic
	);
	END component;

	-- Parte 3.1
	component alarm is
	PORT (
			signal cc: IN std_logic;
			signal m: IN std_logic;

			signal clk: IN std_logic;
			signal reset: IN std_logic;

			signal sirene: OUT std_logic
	);
	END component;



-- Comportamento
BEGIN
	ana: analisa PORT MAP ( ss(2),ss(1),ss(0),m );

	-- Parte 5.2
	alan: alarm PORT MAP ( cc, m, clk, reset, sirene  );

	clk_gen: process
	begin
		clk <= '0';
		wait for 1 ns;
		clk <= '1';
		wait for 1 ns;
	end process;


	reset_gen: process
	begin
		reset <= '1';
		wait for 0.5 ns;
		reset <= '0';
		wait for 19.5 ns;
	end process;


	cc_gen: process
	begin
		cc <= '0';
		wait for 0.5 ns;
		cc <= '1';
		wait for 19.5 ns;
	end process;


	count: process(clk, reset)
	begin
		if reset = '1' then
			state <= "00";
		elsif rising_edge(clk) then
			state <= std_logic_vector( unsigned(state) + 1 );
		end if;
	end process;


	ss_gen: process(clk)
	begin
		if reset = '1' then
			ss <= "000";
		elsif rising_edge(clk) then
			case state is
				when "00" =>   ss <= "000";
				when "01" =>   ss <= "001";
				when "10" =>   ss <= "100";
				when "11" =>   ss <= "011";
				when others =>   ss <= "000";
			end case;
		end if;
	end process;
END;

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