--== Header =============================================================================

library IEEE;
use IEEE.std_logic_1164.all;

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--== Entidade ===========================================================================

ENTITY analisa IS
	PORT (
		signal  s2 :  IN std_logic;
		signal  s1 :  IN std_logic;
		signal  s0 :  IN std_logic;
		signal   m : OUT std_logic
	);
END analisa;

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--== Arquitetura ========================================================================

ARCHITECTURE behavior OF analisa IS
	-- Sinais Locais


-- Comportamento
BEGIN
	m <=  (s2 and s1) or (s0 and s1) or (s0 and s2);
END;

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