--== Header =============================================================================

library IEEE;
use IEEE.std_logic_1164.all;

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--== Entidade ===========================================================================

ENTITY decryptor IS
	PORT (
		byte_entrada : IN std_logic_vector(7 downto 0);
		         clk : IN std_logic;
		       reset : IN std_logic;
		         msg : OUT std_logic_vector(7 downto 0)
	);
END decryptor;

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--== Arquitetura ========================================================================

ARCHITECTURE behavior OF decryptor IS
-- Sinais Locais
	signal state : std_logic_vector ( 1 downto 0 );
	signal senha : std_logic_vector ( 7 downto 0 );

-- Comportamento
BEGIN
	process(clk, reset)
	begin
		if reset = '1' then
			state <= "00";
		end if;

		if rising_edge(clk) then
			case state is
				when "00" =>
					-- Opcao usando case
					case byte_entrada is
						when "00000001" => state <= "01";
						when others     => state <= "00";				
					end case;

					-- Opcao usando if
					--if byte_entrada = "00000001" then
					--else 
					--end if;

				when "01" =>
					state <= "10";
					senha <= byte_entrada;			
				when "10" => 
					state <= "10";
					msg <= byte_entrada xor senha;
			
				when others =>
					state <= "00";
					msg   <= "00000000";
			end case;
		end if;
	end process;

END;

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