Exemplo - Atribuição

Codigo: example_attr.tar.gz

Codigo em VHDL

		
--== Header =============================================================================

library IEEE;
use IEEE.std_logic_1164.all;

-----------------------------------------------------------------------------------------


--== Entidade ===========================================================================

ENTITY Attr_tb IS
END Attr_tb;

-----------------------------------------------------------------------------------------


--== Arquitetura ========================================================================

ARCHITECTURE behavior OF Attr_tb IS
	-- Sinais Locais
	signal a : std_logic;
	signal b : std_logic;
	signal c : std_logic;
	signal t : std_logic;

	signal pa : std_logic;
	signal pb : std_logic;
	signal pc : std_logic;
	signal pd : std_logic;

	signal clk: std_logic;


-- Comportamento
BEGIN
	a <= '1';
	b <= '0';
	c <= a or b;

	process(clk)
	begin
		pa <= c;            -- L1
		pb <= pa;           -- L2
		pc <= pb;           -- L3
		pd <= pa and b;     -- L4

		t  <= a and b;
		t  <= a  or b;
	end process;



-- Nao considerar esta parte
	clk_process: process
	begin
		clk <= '0';
		wait for 1 ns;
		clk <= '1';
		wait for 1 ns;
	end process;

END;

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Circuito Compilado