Codigo: example_case.tar.gz
--== Header ============================================================================= library IEEE; use IEEE.std_logic_1164.all; ----------------------------------------------------------------------------------------- --== Entidade =========================================================================== ENTITY Case_tb IS END Case_tb; ----------------------------------------------------------------------------------------- --== Arquitetura ======================================================================== ARCHITECTURE behavior OF Case_tb IS -- Sinais Locais signal a : std_logic_vector(1 downto 0); signal s1 : std_logic; signal clk : std_logic; -- Comportamento BEGIN a <= "01"; process(clk) begin if a = "00" then s1 <= '0'; else if a = "01" then s1 <= '1'; else s1 <= 'Z'; end if; end if; case a is when "00" => s1 <= '0'; when "01" => s1 <= '1'; when "10" => s1 <= 'Z'; when "11" => s1 <= 'Z'; when others => s1 <= 'Z'; end case; end process; -- Nao considerar esta parte clk_process: process begin clk <= '0'; wait for 1 ns; clk <= '1'; wait for 1 ns; end process; END; -----------------------------------------------------------------------------------------