portas.vhdl

Exemplo de uso de portas com/sem atraso

Para compilar e visualizar a simulação, use o procedimento de compilação, acrescentando a opção '-P/home/html/inf/nicolui/grad/ci068/geral/VHDL/lib' em cada comando 'ghdl'

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-- PACKAGE ci068.portas
-- Exemplo de uso de portas lógicas com/sem atraso
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library IEEE;
use IEEE.std_logic_1164.all;
--
library ci068;
use ci068.portas.all;

entity circuito is
  port( a, b, c: in std_logic;
        f: out std_logic );
end circuito;

architecture comportamento_circuito of circuito is
  signal s1,s2,s3 : std_logic;       

  begin
    comp1 : xor2 port map (a, b, s1);
    comp2 : or2 generic map (delay  => 10 ns ) port map (s1, c, s2);
    comp3 : inv generic map (delay  => 5 ns ) port map (s2, s3);   
    comp4 : and2 generic map (delay  => 10 ns ) port map (s3, b, f);
  end comportamento_circuito;

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library IEEE;
use IEEE.std_logic_1164.all;

entity teste is
end teste;

architecture simulacao of teste is
  component circuito
    port( a,b,c: in std_logic;
          f: out std_logic );
  end component;

  signal a_in, b_in, c_in: std_logic;
  signal f_out: std_logic;
begin
  circ: circuito port map ( a_in, b_in, c_in, f_out);

  a_in <= '0', 
          '1' after 50 ns, '0' after 100 ns, 
          '1' after 150 ns, '0' after 200 ns; 
  b_in <= '1', 
          '0' after 60 ns, '0' after 120 ns, 
          '1' after 160 ns, '0' after 220 ns; 
  c_in <= '0', 
          '1' after 70 ns, '0' after 140 ns, 
          '0' after 170 ns, '0' after 240 ns; 
end simulacao;

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